EXECUTIVE OVERVIEW As we head toward Intel's announced 45nm launch this month, Dick James looks at the changes from the company's 90nm node transistor, through the 65nm node, and take a few guesses about what we might see in the upcoming 45nm part.

After a slow striptease of process announcements, Intel launched the 90nm Prescott chip in January 2004. The chip sported a number of significant process innovations?the first application of strain to transistors in a commercial product (both nMOS and pMOS), the introduction of low-k dielectrics, and the first use of nickel silicide.

The 65nm device came out in late '05, ahead of Intel's two-year cycle, and while there were noticeable differences in structure and process, it was essentially a shrink of the 90nm part. However, they did use a new low-lead package using copper pillars to replace the conventional solder balls. Currently, we anticipate the 45nm generation, with a seminal change of technology from polysilicon gate/silicon dioxide dielectric, to metal gate and high-k dielectric.

First, though, let's start with a short discussion of the use of strain to enhance carrier mobility in silicon. A lot of work was done in the 1990s using a relaxed SiGe substrate to stress an overlying silicon epitaxial layer, and this showed that both the electron and hole mobilities could be enhanced [1, 2]. The mismatch between the larger SiGe lattice and the silicon layer creates biaxial strain, altering the band structure and electronic properties. However, this same mismatch creates a high dislocation density, making the technique incompatible with high-volume manufacturing?as we know, leakage is a big enough problem in deep-submicron technologies, without adding a dislocation-induced component.

Toward the end of the 1990s, attention switched to process-induced uniaxial strain, and it was shown that tensile stress applied along the channel length improved electron mobility, and compressive stress improved hole mobility [3]. The nitride contact etch-stop layer (CESL) laid down on the transistor and sidewall spacers was used to apply the stress.

In addition, it has long been known that mobility is dependent on channel orientation, but since the vast majority of CMOS devices use the standard <110> direction, this has not been used as a performance enhancer.

Intel's 90nm transistor
Intel, of course, had been doing its own research and had noticed the effect of tensile nitride improving nMOS performance in its 130nm product. The company had also been experimenting with embedded epitaxial SiGe pMOS source/drains as a way of reducing S/D resistance because the dopant activation of boron is higher if Ge distorts the lattice. As a result of this work, Intel also found that the embedded SiGe applied uniaxial compressive strain to the channel, improving pMOS performance [4].

At the IEDM meeting in 2002, Scott Thompson presented the first paper [5] on Intel's 90nm process, referring to the use of strained transistors, and discussing the use of nitride and epitaxial SiGe to apply stress, but not giving the specific details as to how it was applied. At the 2003 IEDM, however, Tahir Ghani announced [6] the use of a tensile nitride film to improve nMOS performance, and embedded SiGe source/drains to enhance pMOS devices.

Within weeks, we had our samples in the lab, and had looked at the details of the transistor structure. Figure 1 shows a TEM cross-section of an nMOS transistor; we can clearly see the thicker nitride CESL, ~70nm compared with 25?30nm in pre-strain processes. The minimum gate length we saw was ~45nm. We also measured a gate dielectric thickness of ~1.3nm, which agreed reasonably well with the 1.2nm announced by Intel. We estimated a ~70nm N+ source/drain (S/D) depth, and there was an impressively small ~40nm spacing between the gate edge and the silicide edge.

Intel was the first to move to nickel silicide on the gate and source/drains, and nitride sidewall spacers have also been used. Close examination shows that the buffer oxide between the gate and the spacers has been etched back before formation of the CESL; this may be a side effect of a cleaning step after silicidation, but it has the benefit of getting the stressed nitride layer closer to the channel edge. Intel claimed a mobility increase of ~10% using this process.

Figure 1. Intel's 90nm nMOS.

Figure 2. Intel's 90nm pMOS transistor.

Looking at the pMOS transistor section in Figure 2, the embedded SiGe regions are well delineated, the substrate is isotropically etched out in the S/D regions, and local epi-SiGe (~17% Ge) is deposited into the ~100nm deep cavities. The epi layer has formed crystalline facets to effectively give raised source/drains, reducing the series resistance. The tensile stress from the nitride layer is counteracted by the compressive effect of the SiGe. The pMOS transistors were longer at ~60nm, and the gate edge/silicide distance is ~47nm; mobility enhancement was up to 50%.

The source/drains are likely doped in situ with the SiGe, and also doped by the gate polysilicon implant. As we noted above, the Ge allows higher boron activation, again reducing the series resistance. The SiGe also inhibits the formation of CoSi₂, and since nickel silicide consumes less silicon, forms at a lower temperature, and gave better polycide resistance, nickel was chosen for silicidation.

This image also bears further examination; if we look closely, we can see dislocations at the epi interfaces. A longitudinal section of the embedded epi (Fig. 3) shows a stacking fault initiated at the SiGe/Si interface. These would normally be expected to be a leakage source, but the boron has out-diffused from the epi pockets to contain the defects within the ~120nm deep p+ S/D diffusions and thus neutralize them.

Figure 3. Stacking fault in SiGe layer.

Another noteworthy feature is that the edge of the SiGe facet is displaced from the edge of the spacer, indicating that a sacrificial masking oxide was used. The removal of such an oxide would account for the etch-back at the top of the buffer oxide on the gate sidewalls, and possibly the unusually deep etch-back of the shallow trench isolation (Fig. 4).

Figure 4. pMOS transistor showing STI etch-back.

The 65nm Transistor
After going into some detail on the 90nm transistor structure, let's see what changed as Intel moved to the 65nm version. The nMOS transistor (Fig. 5) shows a number of changes; the CESL now has a multi-layer structure characteristic of Novellus deposition equipment, and is slightly thicker at ~80nm. The nitride sidewall spacers have evolved to a more triangular profile, the buffer oxide is gone, and it appears that the source/drains have been deliberately recessed. The gate height has shrunk from ~130nm to ~75nm, although the polycide is still ~40nm thick; the gate/silicide spacing is similar at ~36nm.

Figure 5. Intel's 65nm nMOS transistor.

The smallest gate length gate we found was ~ 42nm, and the gate dielectric was still 1.3?1.5nm, having hit the leakage barrier?at four or five molecular layers it's not practical to go any thinner! We also noticed stacking faults adjacent to the gate edge, presumably due to higher doping of the S/D extensions. The N+ S/D depth has been scaled to ~50nm.

Intel claims a 20% mobility improvement [7] over the 90nm process using the enhanced strain technology; there is likely higher strain in the CESL, but the thinner and shorter gate electrode, the recessed S/D, and the slightly closer placement of the layer to the channel edge probably intensify the strain along the channel. Reference 7 speaks of "improved thermo-mechanical design of spacers and stress inducing film," so presumably the anneal steps have also been tuned to optimize the strain. A minimum contacted pitch of 220nm was used to ensure that there is sufficient space available to apply the strain; if the nitride does not contact the substrate adequately, the strain will not have the desired effect on the channel.

The pMOS transistor in Fig. 6 illustrates the second-generation embedded SiGe S/D structure. It looks as though the S/D etch was masked by the sidewall spacers this time, and epi growth has continued up the side of the spacers, giving facets as before. The cavity shape was modified and scaled to ~85nm depth; we saw no crystalline defects in the SiGe. The minimum observed pMOS gate length was ~38nm, and the p+ depth was ~90nm.

Figure 6. Intel's 65nm pMOS transistor.

The Ge concentration was raised to ~23%, which, together with the smaller dimensions, improved thermal processing (no defects!) and cavity geometry, increased the strain to give a 30% mobility gain over the 90nm node. The P- substrate epi layer concentration was also increased to ~1×10¹⁶.

Figure 7 is a comparative plot of the transfer characteristics of the Intel transistors versus transistors from two other 65nm generation parts, a Xilinx FPGA fabbed by UMC, and a Matsushita SoC, measured on our in-house nanoprober under high drain bias (|VDD| = 1?1.2 V). This plot clearly shows that the Intel transistors have the highest on-state drive currents (I_ON) of the three devices, as much as twice that of the UMC or Matsushita transistors. However, its off-state leakage currents (I_OFF) are substantially worse, being as much as 100 times greater than either the UMC or Matsushita transistors.

Figure 7. Transfer characteristics of Intel, UMC, and Matsushita 65nm transistors.

Some of the difference is due to the shorter gate lengths of the Intel transistors, in this case ~46nm, compared with 50?55nm for the other two parts. Since I_ON ~1/L, this should not be >20%; at |V_GS| = 1V, the Intel nMOS I_ON is 66?140% greater, and the pMOS transistor I_ON is 150?200% larger, than the UMC and Matsushita devices, respectively. Our structural analyses of these two parts indicate that the UMC process incorporates some strain from dual-stressed CESLs, as well as using rotated wafers to give a <100>-direction channel to improve pMOS performance; but the Matsushita process does not seem to use any mobility-enhancement technique. On this evidence, strain technology works!

What's coming at 45nm?
The guys at Intel have been teasing us again for the last couple of years with pre-announcements of the 45nm process, leaking out deliberately imprecise information that tells us they will be using a hafnium-based high-k gate dielectric with metal gate electrodes. Gordon Moore has blessed the news by marking it as the biggest change in transistor technology since the introduction of polysilicon gates in the late 1960s.

Back in November 2003, Intel made a splash with the announcement that it had identified the elements of a high-k/metal gate transistor, and that the company would be targeting them for its 45nm process to be launched this year [8]. The paper described the use of atomic layer deposition (ALD) to grow the high-k gate dielectric, but no other details; then they went into stealth mode for three years.

Mark Bohr showed off the first 45nm SRAMs, with a 0.346µm² cell size, in January 2006, and the big announcement of high-k/metal gate came a year later at the end of January this year—Intel proudly showed off the world's first working 45nm CPU, made with a high-k/metal gate process. The claimed technology benefits were ~30% reduction in switching power, >20% improvement in switching speed/>5× reduction in S/D leakage, and >10× reduction in gate dielectric leakage. It was also predicted that production would start in the second half of this year.

Not much leaked out since then, until the IEDM 2007 press tip-sheet announced that the process includes "1nm electrically-thick high-k dielectrics; dual-band-edge work function metal gates; trench-contact-based local routing; third-generation strained silicon; nine layers of copper interconnect with a low-k interlayer dielectric; low-cost 193nm dry patterning for critical layers, and lead-free packaging." Which does not say much more, really, except that at 9:30 am on Tuesday, December 11, all will be revealed by Kaizad Mistry and 49 other authors [9] (et al. really means something at Intel!).
Actually, the 50 authors of the IEDM paper really speaks to the complexity of getting a high-k/metal gate process into production. For a literate description of the challenges and process the Intel team have gone through in the last few years, see the article in the October issue of IEEE Spectrum [10]. This article also mentions that fully-silicided polysilicon (FUSI) is not used, and a gate-last process is employed to form the metal gate electrodes.
So, let's summarize what we know:

• Hafnium-based high-k dielectric, 1nm equivalent oxide thickness (EOT), ALD used


• Different metals for nMOS and pMOS gates (not FUSI)


• Gate-last process to form gates


• Strained silicon is still being used

Figure 8 shows Intel's image of its high-k gate stack from the January announcement. Conveniently, it is a high-resolution TEM image, and we can see the (111) crystal planes (assuming the normal <110> channel direction), which allows us to calibrate it, since the (111) spacing is 3.13Å. I have placed a calibrated image on the right, and at least in this sample, it appears that the high-k layer is ~2.3nm thick, and the metal ~5.8nm thick. So if Intel's process uses EOT 1nm, the k-value of the new dielectric is ~9.0, since SiO₂ has a k of ~3.9.

Figure 8. HRTEM images of high-k gate stack.

When it comes to the gate metals, so many variations have been tried that it is almost impossible to make a prediction as to what Intel is using. Just looking at the work functions across the periodic table is no help, since high-k dielectrics (and their methods of formation) alter the work functions, so it really does become a shell game. No wonder it's taken years to get to this point!

For a hint, I checked Intel's patents on metal gates, and they filed a whole bunch at the end of 2003, just after the press announcement. The claims are of course imprecise?it is the job of a good patent lawyer to disclose the invention while giving away as little detail as possible. Scanning through the claims gives us the following:

• High-k dielectric: HfO₂, HfSiO


• nMOS: Zr, W, Ta, Hf, Ti, Al, Metal carbide, transition metal aluminides (e.g. Ti₃Al, ZrAl)


• pMOS: Ru, Pa , Pt, Co, Ni, TiAlN, WCN, metal oxide


• Low resistance layers: TiN, W, Ti, Al, Ta, TaN, Co, Ni

We can rule out HfO₂ for the dielectric since the k-value is too high (25?30); since SiO₂'s k~3.9, presumably the k can be tuned by adjusting the amounts of silicon and oxygen in the layer, either during the ALD process or by subsequent processing. Also, judging by the literature, HfSiON seems to be the consensus dielectric material, with a nominal k of ~12, which can be also tuned by ozonization or nitridation. These patents were filed 3?4 years ago, so it doesn't seem to be an unreasonable guess to suppose that a silicon-rich HfSiO or HfSiON layer could be used here.

A clue may be that the gate leakage reduction is quoted as >10×, whereas HfSiON references typically quote >100× reduction in leakage [e.g. 11]; higher Si content would presumably increase the 'tunnelability' of the dielectric. Most high-k references also discuss using an interfacial monolayer with a high oxygen content, to maintain carrier mobility; this would also reduce the effective k-value.

When it comes to the metals, we should be able to rule out aluminum because of the subsequent thermal processing, but that still leaves us quite a few alternatives. The use of carbides, aluminides, and oxides is an interesting reflection of the variety of different materials investigated by Intel.

Figure 9 below shows the gate-last structure from US patent 7,157,378, which agrees with the layer structure in Figure 8. Features 115 and 119 are the high-k dielectric, 116 and 120 are the work function metals, and 121 and 118 are the low resistance layers. The remaining features 101 and 102 are the substrate wells, 103 the isolation, and 112 a dielectric layer.

Figure 9. Intel gate-last structure.

This structure requires complex processing; conventional n- and p-doped polysilicon gates are formed, and used as sacrificial structures to form trenches into which the high-k/metal gates are filled and polished back. The use of n- and p-poly allows them to be etched independently, so that each metal gate stack can be formed separately, including the high-k dielectric and low-resistance layers, if desired. However, all the extra processing steps seem to be etch/deposit/polish; no additional masks are needed.
I will pass on trying to make an educated guess at the work-function metals, since I have no information on the interaction of the multiple candidates with the possible dielectrics?those of you in the fabs working in the technology will have a much better idea!

Of the possible low-resistance filler metals, tungsten, tantalum, and titanium and tantalum nitride are the ones that appeal, simply because the CMP of them is already well established in manufacturing. Of course, there may also be interactions with the work-function metals that limit the field, so again it is difficult to make a solid prediction.

Intel has also said that third-generation strain will still be used to enhance mobility; this is actually more necessary with the new structure, as even well-engineered high-k layers inhibit mobility compared with SiO₂. That means that dielectric 112 will have to be etched back to expose the sidewall spacers, so that the stressed nitride can be applied. The source/drain implants (and embedded SiGe, if it is used) could have been done using a normal process sequence after defining the sacrificial poly gates, as the sidewall spacers are about the only parts of the structure in this sequence that stay there.
So, apart from the ground-breaking materials technology, with all the extra fabrication steps indicated above, we could also regard the 45nm node as a new level of process complexity. We'll find out how much more at IEDM!

References
1. K. Rim, et al., "Enhanced Hole Mobilities in Surface-Channel Strained-Si p-MOSFETs," International Electron Devices Meeting Technical Digest, pp. 517?520, 1995.
2. K. Rim, et al., "Transconductance Enhancement in Deep Submicron Strained-Si n-MOSFETs," International Electron Devices Meeting Technical Digest, pp. 707?710, 1998.
3. A. Shimizu, et al., "Local Mechanical-Stress Control (LMC): A New Technique for CMOS-Performance Enhancement," International Electron Devices Meeting Technical Digest, pp. 433?436, 2001.
4. "The Invention of Uniaxial Strained Silicon Transistors at Intel," http://electronics.wesrch.com/Paper/display_pdf.php?pdf_file=2_1170790373.pdf.
5. S. Thompson, et al., "A 90nm Logic Technology Featuring 50nm Strained Silicon Channel Transistors, 7 Layers of Cu Interconnects, Low-k ILD, and 1µm² SRAM Cell," International Electron Devices Meeting Technical Digest, pp. 61?64, 2002.
6. T. Ghani, et al., "A 90nm High-volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors," International Electron Devices Meeting Technical Digest, pp. 978?980, 2003.
7. S. Tyagi, et al., "An Advanced Low-power, High-performance Strained Channel 65nm Technology," International Electron Devices Meeting Technical Digest, pp. 1070?1072, 2005.
8. R.Chau et al., "Gate Dielectric Scaling for High-performance CMOS: from SiO₂ to High-k," International Workshop on Gate Insulator, pp. 124?126, November 2003.
9. K. Mistry et al., "A 45nm Logic Technology with High-k+ Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging," International Electron Devices Meeting Technical Digest, paper 10.2, 2007.
10. M. Bohr et al., "The High-k Solution," IEEE Spectrum, pp. 29?35, October 2007.
11. M.A. Quevedo-Lopez et al., "High-performance Gate-first HfSiON Dielectric Satisfying 45nm Node Requirements," International Electron Devices Meeting Technical Digest, pp. 437?440, 2005.

DICK JAMES is a 30-year veteran of the semiconductor industry and the senior technology analyst for Chipworks, an Ottawa, Canada-based specialty reverse engineering company that gets inside technology and takes apart ICs and electronics systems in order to provide engineering information for its customers. Contact him at 3685 Richmond Road, Suite 500, Ottawa, ON, K2H 5B7, Canada; ph 613/829-0414, fax 613/829-0515, djames@chipworks.com, www.chipworks.com.