Marc D. Himel, James T. A. Carriere, Tessera N. America F.M. Schellenberg, Y. Granik, Mentor Graphics

Diffractive optical elements improve imaging by optimizing the illumination for critical mask patterns without excessive loss of light.

Among the innovations in lithography that enable pursuit of Moore’s Law into the sub-wavelength realm is off-axis illumination (OAI), which shapes illuminator optics so that light falling on the photomask has certain angles emphasized at the expense of others (with light at normal incidence, “on-axis” significantly reduced or absent). This is typically represented by a diagram (Fig 1.) in the pupil plane of the optical system, where the x-y position corresponds to a certain angle of incidence, with the center representing normal incidence and the outer ring, the limit dictated by the lens NA.

Initially, OAI patterns were created by placing a hard-stop aperture in the illumination system. This had several problems, most notably that the aperture plate loses a significant portion of the light. Diffractive optical elements (DOEs) are routinely used for situations where the light needs to be significantly shaped, yet low loss is desirable. With a suitable DOE design, diffraction efficiencies above 83% can be achieved. [1]

Another crucial innovation was the adoption of design-for-manufacturing (DFM) methodologies, such as optical & process correction (OPC) and phase-shifting masks (PSMs). [2] For these techniques, the optical deficiencies of the patterning system are simulated computationally, and changes are made to layout patterns on the photomask that compensate for these distortions. In this manner, the photomask becomes not a passive shadow mask, but an optical element in the path from light source to wafer. [3]

Source ? Mask Optimization (SMO)

The RET computations assume some OAI, generally those specified by the scanner manufacturer. However, it was recognized that some of these illumination patterns, while favoring certain geometries, introduced forbidden pitches that were more difficult to image.[4] Furthermore, while an ideal source map might be a worthy goal, real source maps (Fig. 1) can be quite different, causing significant corrections to be made on the photomask. For the particular example in Fig. 1c, feature placement changes by ~17nm were made to compensate for the real scanner configuration.[5]

Since the OPC features can be adapted to the actual source used, optimization procedures can be extended to include optimizing the source for the particular layout pattern on the photomask. The repetitive layout patterns of DRAM limit spatial frequencies in the image, facilitating the customization of the source illumination using standard OPC methods. [6]

Initial customization adapted an existing OAI geometry and modified the parameters through optimization, such as tuning inner and outer σ values for annular illumination. As features continue to shrink and the wavelength remains at λ=193 nm, the need for source optimization is more pronounced. This leads to a pixel-based approach for source optimization, in which a variety of grey levels for individual points in the source map can be specified. [7] This allows both pixelated sources and photomasks to be generated.

With a pixel grid for both mask and source specified, co-optimization is possible. Starting with an initial guess for the source and mask, the values for individual pixel grids can be optimized in parallel; with a first iteration for the source, and then an additional iteration for the photomask, until convergence to a corrected photomask layout and corresponding source map is achieved.

Creation of a DOE

Once this grey-scale OAI source map has been generated, the diffractive optical element (DOE) that can produce this pattern must be created. This procedure is essentially the formation of a computer-generated hologram (CGH) that diffracts light to form the desired illumination pattern.

As an illustration, we will initially consider the design for a DOE with a circular output pattern. The desired numeric aperture (NA) typically describes the angular extent of a DOE output pattern. The NA of a pattern is the sine of the half-angle over which the light will be spread (sin θ= NA). From this initial specification, we can determine some important properties of the DOE. The ideal DOE is aperiodic; the pattern of the DOE does not repeat itself for a relatively large transverse distance. However, the element does contain the correct range of spatial frequencies to produce the desired diffraction pattern within a finite length, or pseudo-period. This pseudo-period can be determined using the grating equation:

d sin θ= mλ

where d is the period of the grating, λ is the wavelength of light used, m is the desired diffraction order from the grating, and θ is the angle at which the desired order is deflected. To determine the pseudo-period of the DOE, we set m=1. The separation between diffraction orders is linear in sin θ. If the imaging system does not use an fsin θ lens, the final illumination pattern could be distorted.

To create a circular DOE with an NA of 0.025 for use at λ=193nm, we create a circular target grid with a radius of, say m=100 orders From our grating equation we determine that the pseudo-period (m=1) in this DOE is 772µm. This dimension determines the angular separation between diffraction orders, and that the source map can be defined by specifying the relative intensity (typically 0 ? 255 intensity levels) of the light diffracted into each diffraction order. When the DOE is designed, it will diffract most of the incident light into the target diffraction orders. By selecting a reasonably high value for m, we ensure that the angular separation between orders is small relative to the source divergence of an excimer laser.

For DOEs used for OAI in 193nm scanners, we have found that the best balance between coherent artifacts (or speckle), design flexibility, and computation time occurs when we use between 101 and 251 diffractive orders across the source map. The exact number of diffractive orders across the NA is dependent on the specifics of the scanner’s illumination system. To achieve ease-of-fabrication and most accurate match to the desired source map, it is best if the source map produced by SMO routines maps directly into our target grid.

Fabrication and verification of the DOE

The critical performance parameters of a DOE are intensity uniformity, residual zero order, NA matching, stray light, and part-to-part repeatability. All can vary with the fabrication process. Tessera North America’s standard manufacturing approach utilizes stepper-based lithography for multilevel diffractive element fabrication. Starting with an E-Beam generated mask set, a DOE is fabricated by sequentially aligning, exposing, developing, and etching successive pattern layers into an excimer-compatible substrate. [8] One of the primary advantages of this approach is the process repeatability. Because our diffractive design and fabrication approach is based on discrete levels with well defined features, the angular output is extremely repeatable.

As 193nm lithography is pushed to the limits, the ability of the DOEs fabricated performance to match the source map specification will become increasingly important. To demonstrate our capability with more advanced grey-tone designs, we created a test pattern, shown in Fig. 2, to both demonstrate our ability to match the design parameters and the repeatability of our process. The varying and continuous grey scaled regions of this pattern make it very challenging to design and fabricate the corresponding DOE.

Despite the complex nature of the pattern, the experimental cross-section of the output intensity pattern for an average of 20 measured manufactured units (Fig. 3) demonstrates the capability of the Tessera process to simultaneously achieve multiple intensity level targets within the same DOE design. For the discrete intensity levels in this source map, we found that the worst case deviation from the design was 6.2% with an average deviation from target of 1.85%. The uniformity within a zone was found to be within ±4%. Similarly, the average difference between measured and target for the sloped regions was 4.7% with a maximum deviation of 7%. These results suggest that although we can and should design with 255 grey levels, the number of grey levels needed to be effective may be as low as 64.

Equally important to this is part-to-part repeatability. Figure 3b shows the DOE output-intensity patterns for 20 different manufactured units on five wafers, along with their pixel-by-pixel standard deviation. For this complex example, the average standard deviation is 4%, showing quite good repeatability. One of the critical performance parameters for OAI is the NA matching between parts. Figure 3b also shows the repeatability of the inner and outer sigma for the various zones or poles. Notice that the edge transitions for all 20 samples line up perfectly.

An example of SMO

Figure 4 shows a layout for an SRAM cell, and the corresponding ideal grey scale illuminator source map generated by a Mentor Graphics SMO procedure. Because this pattern has roughly 10 bright regions, we have nicknamed it a decapole pattern. The method used to co-optimize the mask and illumination was published previously in detail and will not be repeated here. [9]

Beginning with this decapole source map, we created the eight-level DOE design necessary for its fabrication. A Tessera far-field optical simulator was used to predict the DOE output expected once this has been manufactured. The output of this simulation reproduces the desired source map quite well (Fig. 4). Figure 5 compares the expected performance of this optimized source and the standard annular illumination at a particular cross section through the layout. It is clear that the decapole offers a much better image slope and modulation, and thus an enhanced process window.

Summary

At this point, the technology for co-optimization of OPC photomasks and pixelated source maps exists and has been demonstrated. Image fidelity improvements for examples of certain cells have been demonstrated, and the limitations that result from the stepwise DOE manufacturing process can be managed.

It remains an economic question whether the work involved in optimizing the illuminator and managing the insertion into the scanner of customized DOEs that correspond to particular photomasks will be worthwhile. If the image fidelity that can be achieved will allow a single exposure to produce patterns that otherwise require double patterning, the improvement in tool utilization will make that a resounding, yes. If, on the other hand, customized patterns only allow a moderate improvement for layout with a wide variety of feature sizes and pitches, results will have to be evaluated case by case.

The trend, however, in IC layouts for 32nm and 22nm designs is to follow more restrictive design rules (RDRs), i.e. using only certain gate dimensions and pitches. [10] We expect the additional constraints this places on the ultimate dimensions on the wafer to make the utility of customizing the illuminator and mask structures to be more, not less, economical. Although currently only the mask layout and source map are co-optimized, we expect that eventually this co-optimization procedure will be expanded to include all constraints affecting the image, including constraints for the wafer, photomask, source map, and DOE. Although complex, the tools demonstrated here show this to be an achievable goal, and the fabrication procedures for customized DOEs are currently available for utilization today.

References

1. J. L. Leonard, J. Carriere, R. Jones, M. Himel, J. Stack, and J. Childers, “An improved process for manufacturing diffractive optical elements (DOEs) for off-axis illumination systems,” Proc. SPIE 6924-97 (2008).
2. A.K.K. Wong, Resolution Enhancement Techniques in Optical lithography (SPIE Press, Bellingham, WA, 2001).
3. Y. Granik, “Fast pixel-based mask optimization for inverse lithography” J. Microlith., Microfab., Microsyst. 5, 043002 (2006).
4. R. J. Socha, M. V. Dusa, L. Capodieci, J. Finders, J. Fung Chen, D. G. Flagello, and K. D. Cummings , “Forbidden pitches for 130-nm lithography and below” Proc. SPIE 4000, 1140 (2000).
5. Y. Granik, N. Cobb, “New process models for OPC at sub-90nm nodes” in Optical Microlithography XVI, Proc SPIE Vol. 5040 pp. 1166-1175 (2003).
6. A. E. Rosenbluth, S. Bukofsky, C. Fonseca, M. Hibbs, K. Lai, A. F. Molless, R. N. Singh, and A. K. K. Wong, “Optimum mask and source patterns to print a given shape”, J. Microlithogr. Microfabrication, Microsyst. 1, 13 (2002).
7. Y. Granik, “Source optimization for image fidelity and throughput” J. Microlithogr. Microfabrication, Microsyst. 3, 509 (2004).
8. M. D. Himel, R. E. Hutchins, J. C. Colvin, M.s K. Poutous, A. D. Kathman, and A.S. Fedor , “Design and fabrication of customized illumination patterns for low-k1 lithography: a diffractive approach” Proc. SPIE 4346, 1436 (2001).
9. Y. Granik, “Source optimization for image fidelity and throughput” J. Microlithogr. Microfabrication, Microsyst. 3, 509 (2004).
10. T. Jhaveri, et al. , “Maximization of layout printability/manufacturability by extreme layout regularity” J. Micro/Nanolith. MEMS MOEMS 6, 031011 (2007).

Contact: Marc D. Himel, PhD, MBA, Tessera North America, 9815 David Taylor Drive, Charlotte, NC 28031; Phone: 704.887.3162; FAX: 704.887.3101: e-mail: mhimel@tessera.com

Biographies:

Dr. Himel received his BS degree in Physics from the California Polytechnic State University in 1984, his PhD in Optical Sciences from the University of Arizona in 1988, and an MBA from the University of Connecticut in 1998. For 14 years, he has worked in the design and development of advanced lithography systems at AT&T Bell Laboratories, SVG Lithography Systems and Tessera North America. Dr. Himel is currently a Senior Principal Engineer at Tessera North America.

Dr. Carriere is a senior optical engineer at Tessera, where he plays a key role as the technical lead for all semiconductor lithography products. At Digital Optics Corporation he had served as an optical engineer supporting the semiconductor equipment platform. Carriere holds a bachelor’s degree in physics from McGill University in Montreal and both a master’s degree and a doctorate in optical sciences from the University of Arizona.

Frank Schellenberg received his Ph.D. from Stanford University in Applied Physics. Since 1991 he has worked in resolution enhancement technologies (RET) for lithography at the IBM Almaden Research Lab, HP Labs and SEMATECH, and at KLA Tencor, on photomask technology and analysis. In 1998, he joined OPC Technologies, now Mentor Graphics, where he continues to work today.

Yuri Granik received his MS in applied mathematics/computer science and PhD in theoretical physics from Odessa State University, Ukraine. In 1991 he joined Technology Modeling Associates, Inc. He is currently principal engineer in the Calibre division of Mentor Graphics Corp., responsible for the process and OPC simulations and modeling.